1. Field of the Invention
The present invention relates to an emitter coupled logic (ECL) to complementary metal oxide semiconductor (CMOS) translator, and more particularly, to an improved high speed, low power ECL-to-CMOS translator which is impervious to changes power supply, operating temperature and process variations.
2. Description of the Prior Art
With the introduction of BiCMOS technology, which combines the advantages of both bipolar and CMOS technologies on a single semiconductor integrated circuit (IC), ECL-to-CMOS translators are required to translate signals from ECL logic levels to CMOS logic levels.
FIG. 1 shows a block diagram of a conventional ECL-to-CMOS translator 10. The ECL-to-CMOS translator 10 includes a first node (1) coupled to Vss (ground), a second node (2) coupled to receive an ECL input signal [Din] from an ECL circuit 12, a third node (3) coupled to receive a complementary ECL input signal Din from the ECL circuit 12, a fourth node (4) coupled to provide a CMOS output signal [Dout] to a CMOS circuit 14, and a fifth node (5) coupled to provide a complementary CMOS output signal Dout to the CMOS circuit 14.
During operation, the ECL-to-CMOS translator 10 converts the complementary ECL input signals received at nodes (2) and (3) to complementary CMOS output signals provided at nodes (4) and (5), respectively.
ECL circuits typically operate between a five volt differential and have a logic swing ranging from 0.7 volts below the upper potential to 2.0 volts above the lower potential. For example, if the voltage differential is set at a low of -5.0 volts (Vee) to a high of 0.0 volts, then a signal having a potential ranging from -0.7 volts to 0.0 volts is a logical high ("1") and a signal having a potential ranging from -3.0 volts to -5.0 volts is a logical low ("0").
CMOS circuits typically operate between a five volt differential and have a 2 volt logic swing ranging from 1.5 volts below the upper potential to 1.5 volts above the lower potential. For example, if the voltage differential is set at a low of 0.0 volts to a high of 5.0 volts, then a signal having a potential from 3.5 to 5.0 volts is a logical high ("1") and a signal having a potential ranging from 0.0 to 1.5 volts is a logical low ("0").
FIG. 2 shows a prior art circuit implementation of an ECL-to-CMOS 20 translator that is consistent with the FIG. 1 block diagram. In general, the circuit 20 includes a first stage level shifter 22, a second stage level shifter 24, a current gain stage 26 and a basic CMOS invertor 28.
The first stage level shifter 22 translates the ECL level signal [Din] at node (2) into an intermediate CMOS level signal at node (6) through the operation of input transistor M1, M2 and M3. As input signal Din switches from high to low, the potential applied to the gate of transistor M3 is reduced, thereby decreasing the conductance of transistor M3. As a result, the potential at node (7) is pulled down. Transistor M5 acts like a capacitor, storing charge at node (7). As input signal Din switches from high to low, the charge on the gate of transistor M5 is reduced, thereby decreasing the potential at the gate of transistor M5. Thus, transistors M3 and M5 complement one another to pull down node (7). Transistor M6 acts as a resistor at node (8) coupled to the gate of transistor M4. The resistance at node (8) tends to control the conductance of transistor M4, thereby controlling how far node (7) is pulled down.
Conversely, as input signal [Din] switches from low to a high state, a higher potential is applied to the gate of input transistor M1. As a result, transistor M1 is turned on hard. The greater conductance of transistor M1 tends to pull up node (6). Because node (7) is simultaneously pulled down, the potential at the gate of transistor M2 is reduced. As a result, transistor M2 assists transistor M1 in pulling up node (6) to an intermediate CMOS signal level.
Gain stage 26 translates the intermediate CMOS level potentials at nodes (6) and (9) to full CMOS logic levels. With node (6) pulled up to the first intermediate CMOS potential, an increased potential is applied to the gate of N-channel transistor M11, the drain of which is coupled to the gate of P-channel transistor M9. As a result, transistor M11 turns on hard, thereby pulling node (10) down to Vss. With node (10) pulled down, P-channel transistor M10 is turned on hard. With node (6) coupled to the gate of transistor M8, and with node (6) being pulled up to an intermediate CMOS level, the potential at node (9) falls towards Vss. Transistors M10 and M12 cooperate with one another to pull up output signal [Dout] at node (4) to its full CMOS logic level.
CMOS invertor 28 receives the full CMOS logic level signal at node (4) and inverts it at node (5) to provide complementary signal Dout, thus completing the ECL to CMOS translation.
Alternatively, in the event that the ECL input signals [Din] and Din switch from high to low and low to high respectively, transistors M1 through M14 operate in the complement of one another. As a result signal [Dout] is pulled down and signal Dout is pulled up.
The prior art ECL-to-CMOS translator 20 described above has a number of deficiencies. First, during DC operation, an intermediate voltage is constantly being applied to the gates of transistors M1-M12. As a result, transistors M1-M12 are always on, conducting current and dissipating power. During non-switching operation of the ECL-to-CMOS translator 20, approximately 5-10 mA of current is dissipated, depending on the output state.
Another problem occurs during the AC switching operation of the ECL to CMOS translator 20. During a switching operation, all of transistors M1-M14 are in transition from one state to another. Accordingly, each of the transistors M1-M14 consumes more current than when in the non-switching state. During switching, the ECL-to-CMOS translator 20 dissipates approximately 21 mA of current.
Yet another problem of the ECL-to-CMOS translator 20 is that its fourteen transistors M1-M14 require a period of time to complete the switching operation, which is too slow for many BiCMOS product applications.
Finally, with fourteen transistors, the ECL-to-CMOS circuit 20 is impractical for modern high density BiCMOS products. For example in a 1 Meg BiCMOS SRAM, there are at least twenty ECL to CMOS transistors that would consume, worse case, 10 mA*20=200 mA DC power just for the inputs. Also, it would create space and layout problems and reduce product yields, all of which would render the manufacture of such a device economically unfeasible.